1. Field of the Invention
The present invention relates to a method of manufacturing a MOS type semiconductor device such as an insulated gate bipolar transistor (IGBT) used in power conversion devices.
2. Description of the Related Art
The following shows an outline of wafer processing in a method of manufacturing an IGBT having a MOS gate structure of a planar type or a trench type. A semiconductor substrate, which is a wafer, has a thickness of about 500 μm at the beginning of the wafer processing, whereas the thickness of the wafer is finally reduced to a value between 50 μm and 200 μm depending on the withstand voltage of the semiconductor device for a withstand voltage class of 600 V to 1,200 V. A non-punch-through (NPT) IGBT 100 of a planar gate type as shown in FIG. 6 has a semiconductor functional structure in one of the principal surface regions (the upper surface region in FIG. 6) of an n type floating zone (FZ) silicon semiconductor substrate 101. The semiconductor functional structure comprises: a p base region 102, a gate oxide film 103, a gate electrode 104, an n+ emitter region 105, an interlayer dielectric film 106, and an emitter electrode 107. On the rear surface side, after the thickness reduction process and surface treatment, formed are a p+ collector layer 108 with a thickness of at most about 1 μm and a collector electrode 109. Thus the wafer processing in the manufacturing procedure for an IGBT 100 is completed.
On the other hand, a reverse-blocking IGBT 200 of a withstand voltage class of 1,200 V has, as shown in FIG. 13, an isolating diffusion layer 231 differently from the general IGBT 100 shown in FIG. 6. The isolating diffusion layer 231 is provided in order to enhance reliability of a reverse-blocking voltage (or a reverse withstand voltage) and the isolating diffusion layer 231 extends a reverse-blocking junction 207 to the substrate surface, which is protected with an oxide film, whereas the end of the reverse-blocking junction 207 is exposed to the sliced side surface of the substrate in the general IGBT 100. The reverse-blocking IGBT 200 is manufactured by the same procedure as the one for the general IGBT 100 excepting the process of forming the isolating diffusion layer 231, which will be described below.
An initial oxide film is formed as shown in FIG. 11 on a surface of an FZ n type silicon substrate 201, and in the initial oxide film an opening 220 is formed. Ion implantation of p type impurity boron is conducted through the opening 220 in the initial oxide film used for a mask. After removing the initial oxide film, heat treatment in an oxidizing atmosphere is conducted at a high temperature of 1,300° C. for a long time of 300 hr to 330 hr to form a boron diffusion layer as shown in FIG. 12 having a depth of 220 to 230 μm that is to be used as an isolating diffusion layer 231.
After that, as in the general IGBT 100, a semiconductor functional structure in the front surface side is formed comprising: a p base region 202, an n+ emitter region 203, a gate oxide film 204, a gate electrode 205, an interlayer dielectric film 206, and an emitter electrode 209 as shown in FIG. 13. Likewise in the rear surface side conducted are thickness reduction and formation of a p+ collector layer 210 and a collector electrode 211. Thus, a reverse-blocking IGBT 200 is manufactured as shown in FIG. 13.
The general IGBT 100 exhibits a tradeoff relationship between an ON voltage and a turn-off loss. In some cases, an adjustment is demanded to achieve a higher speed and lower loss at the expense of the ON voltage, which means a larger ON voltage. In that case, the process conditions are to be controlled with the thickness of the p+ collector layer 103 to be thin and the impurity concentration therein to be low so that the injection of minority carriers (positive holes) from the p+ collector layer 108 is decreased in a forward-biased period.
In the NPT IGBT 100, the drift layer 101 is made sufficiently thick so that the depletion layer 110 extending from the junction 102a of the p base region 102 into the drift layer 101 on application of OFF time voltage does not arrive at the p+ collector layer 108, which means punch-through does not occur. As a consequence, the ON voltage of the NPT IGBT 100 increases. There is another problem of large turn-off loss due to increased reverse recovery current caused by increase in carriers accumulated in the emitter side of the drift layer 101 in the turn-off time when the total amount of impurities in the p+ collector layer 108 is large.
Concerning an IGBT having this construction, Japanese Unexamined Patent Application Publication No. 2006-080269 (Patent Document 1) discloses a low injection reverse-blocking IGBT that uses a wafer having a gradient distribution of oxygen concentration, in which oxygen concentration gradually decreases from a region of solid solution limit in the bulk to the wafer surface region. The oxygen has been introduced up to a concentration of solid solution limit with a flat distribution in whole the wafer by driving diffusion process in an oxygen atmosphere for about 100 hr, and then partly removed by outward diffusion from the substrate surface in the cooling down process.
Japanese Unexamined Patent Application Publication No. 2004-186620 (Patent Document 2) discloses a punch-through type IGBT in which the oxygen introduced into the bulk of a substrate up to a concentration of the solid solution limit is used for donors after heat treatment to form a high concentration n type buffer layer in the collector layer side of the n type drift layer. In the process of manufacturing this IGBT, the oxygen is introduced into the semiconductor wafer by heat treatment in an oxygen atmosphere at a temperature between 1,150° C. to 1,350° C., and then the introduced oxygen in the surface region is removed by heat treatment in an oxygen atmosphere at a lower oxygen concentration to obtain an oxygen concentration profile of two stage distribution.
Japanese Unexamined Patent Application Publication No. 2006-080269 (Patent Document 1 herein) relates to Paragraph 0005 and FIG. 2 in particular. Japanese Unexamined Patent Application Publication No. 2004-186620 (Patent Document 2 herein) relates to Claim 5 and the Abstract in particular.
However, in an attempt to reduce the turn-off loss, if the impurity concentration in the collector layer of the IGBT is further decreased, this is liable to increase variation of the ON voltages. Thus, it is generally difficult to control the collector layer to a lower concentration than in conventional technologies. It is also difficult to reduce the turn-off loss in a stable manner by means of decreasing the collector layer thickness, because the collector layer thickness has been decreased nearly to the lower limit.
The present invention has been made in view of the problems described above and an object of the present invention is to provide a method of manufacturing a MOS type semiconductor device that achieves small turn-off loss and little variation of ON voltages without controlling a collector layer to a lower concentration than the conventional technology.